PART |
Description |
Maker |
IS61LPD51218T/D IS61LPD25632T/D IS61SPD25632T/D IS |
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM 256K × 3256K × 3612K采样× 18 SYNCHRONOU?管道,双循环取消选择静态RAM 256K X 36 CACHE SRAM, 3.5 ns, PQFP100 TQFP-100 256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM
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Integrated Silicon Solution, Inc. Integrated Silicon Solution Inc
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WEDPZ512K72V-150BI WEDPZ512K72V-150BM WEDPZ512K72V |
512K x 72 Synchronous Pipeline Burst ZBL SRAM
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WEDC[White Electronic Designs Corporation]
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WEDPZ512K72S-150BC WEDPZ512K72S-150BI WEDPZ512K72S |
512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM
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WEDC[White Electronic Designs Corporation]
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WED2ZLRSP01S42BC WED2ZLRSP01S50BI WED2ZLRSP01S38BC |
512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM
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WEDC[White Electronic Designs Corporation]
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AS5SP512K36DQ AS5SP512K36DQ-30ET AS5SP512K36DQ-30I |
Plastic Encapsulated Microcircuit 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
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Austin Semiconductor
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4559 M34559G6-XXXFP |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 单芯位微机的CMOS
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Renesas Electronics Corporation. Renesas Electronics, Corp.
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M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation. Renesas Electronics, Corp.
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AS7C33128PFD36A-166TQI AS7C33128PFD32A AS7C33128PF |
3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 150MHz 3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 133MHz 3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 100MHz 3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 166MHz 3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 150MHz 3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 133MHz 3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 100MHz 3.3V 128K X 32/36 pipeline burst synchronous SRAM 128K X 32 STANDARD SRAM, 10 ns, PQFP100
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Alliance Semiconductor, Corp. ALSC[Alliance Semiconductor Corporation] Alliance Semiconductor Corp...
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AS7C3256PFD18A-4TQC AS7C3256PFD16A-4TQC AS7C3256PF |
3.3V 256K x 16 pipeline burst synchronous SRAM, 150 MHz 3.3V 256K x 16 pipeline burst synchronous SRAM, 100 MHz 256K X 18 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100 256K X 16 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100 3.3V 256K x 16/18 pipeline burst synchronous SRAM 3.3V 256K x 18 pipeline burst synchronous SRAM, 166 MHz 3.3V 256K x 18 pipeline burst synchronous SRAM, 150 MHz 3.3V 256K x 18 pipeline burst synchronous SRAM, 133 MHz 3.3V 256K x 18 pipeline burst synchronous SRAM, 100 MHz 3.3V 256K x 16 pipeline burst synchronous SRAM, 133 MHz 3.3V 256K x 16 pipeline burst synchronous SRAM, 166MHz
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Alliance Semiconductor, Corp.
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AS7C33128PFS32B AS7C33128PFS32A |
(AS7C33128PFS32A / AS7C33128PFS36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
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Alliance Semiconductor Corporation
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CY7C1461AV33-100AXC CY7C1463AV33-100AXC CY7C1461AV |
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL垄芒 Architecture 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(带NoBL结构6-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM) 36兆位米x 36 / 2 M中的x 18/512K × 72)流体系结构,通过与总线延迟(带总线延迟结构的的36 - Mbit通过的SRAM100万x 36 / 2 M中的x 18/512K × 72)流的SRAM
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Cypress Semiconductor Corp.
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AS7C25512FT32_36A AS7C25512FT32A-10TQC AS7C25512FT |
2.5V 512K x 32/36 flowthrough burst synchronous SRAM 512K X 36 STANDARD SRAM, 8.5 ns, PQFP100 2.5V 512K x 32/36 flowthrough burst synchronous SRAM 512K X 32 STANDARD SRAM, 10 ns, PQFP100 2.5V 512K x 32/36 flowthrough burst synchronous SRAM 512K X 32 STANDARD SRAM, 8.5 ns, PQFP100 DIODE ZENER SINGLE 1000mW 47Vz 5.5mA-Izt 0.05 5uA-Ir 35.8Vr DO41-GLASS 5K/REEL Sync SRAM - 2.5V 2.5V 512K x 32/36 flowthrough burst synchronous SRAM
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Alliance Semiconductor, Corp. Alliance Semiconductor Corporation ALSC Alliance Semiconductor ...
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